WHITEPAPER
Per-Model ASIC: The XgenSilicon Approach
Technical foundations of the TrueASIC platform — Model–Software–Hardware Co-Design methodology, AI Architecture Search, and the Model-Aware Compiler stack explained in full.
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Research papers, industry articles, and updates from the XgenSilicon team on edge AI silicon, Model–Software–Hardware Co-Design, and custom ASIC development.
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Latest Highlights
ARXIV
Closing the loop: AI designs the hardware it runs on
An exploration of AI-driven approaches to the full ASIC design flow — from model specification to silicon — and how Model–Software–Hardware Co-Design changes what is possible at the edge.
Read Full ArticleARXIV
Hardware-Aware NN Compilation with LearnedOptimization
AI-driven optimization techniques for neural network compilation targeting edge ASICs — and how co-designing the compiler with the target silicon changes the efficiency equation.
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All Posts
WHITEPAPER·
Per-Model ASIC: The XgenSilicon Approach
Technical foundations of the TrueASIC platform — Model–Software–Hardware Co-Design methodology, AI Architecture Search, and the Model-Aware Compiler stack explained in full.
ARXIV·
Closing the loop: AI designs the hardware it runs on
An exploration of AI-driven approaches to the full ASIC design flow — from model specification to silicon — and how Model–Software–Hardware Co-Design changes what is possible at the edge.
ARXIV·
Hardware-Aware NN Compilation with LearnedOptimization
AI-driven optimization techniques for neural network compilation targeting edge ASICs — and how co-designing the compiler with the target silicon changes the efficiency equation.
PRESS·
Why ASIC Design Makes Sense for LLM On-Device
EE Times examines the case for custom silicon in on-device LLM inference — and why the economics and performance constraints of edge AI are driving a new wave of ASIC design.
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